It is well known that integrated circuit fabrication on semiconductor wafers requires the formation of precisely controlled apertures, such as contact openings, that are subsequently filled with a conductive metal and interconnected to create components and very large scale integrated (VLSI) or ultra large scale integrated (ULSI) circuits. The methods for defining and forming such openings are equally well known to those who are skilled in the art. Market demands for faster and more powerful integrated circuits have resulted in significant growth in the number of devices per cm2, i.e., a higher packing fraction of active devices. This increased packing fraction invariably means that the interconnections for ever-more-complicated circuits are made to smaller dimensions than before. Thus the aspect ratios of the contacts, i.e., the ratio of the opening depth to the opening diameter, have increased from an order of about 1:1 or 2:1 to a present order of from about 3:1 to as high as about 5:1 for sub-0.25 micron devices.
In the past, aluminum (Al) was deposited in the contact openings over a barrier layer to form contacts. However, some fabrication processes, especially those used to produce CMOS and bipolar semiconductors, now use tungsten (W) deposited within the contact opening over an adhesion/barrier layer of titanium/titanium nitride (Ti/TiN). Such adhesion/barrier layers are needed because of the extremely poor adhesion of tungsten applied by chemical vapor deposition (CVD) on such dielectrics as borophosphosilicate glass (BPSG), silicon dioxide, thermal oxide, and plasma-enhanced oxide and silicon nitride. However, it is known that tungsten adheres well to TiN and that TiN adheres well to Ti and that Ti, in turn, adheres well to the dielectrics listed. Thus, a method that achieves good adhesion of CVD tungsten to the substrate is achieved by interposing layers of titanium and titanium nitride between the dielectric and the tungsten plug.
Referring now to FIG. 1A, illustrated is a sectional view of a contact opening 110 formed in a dielectric 101 of a conventional semiconductor wafer 100. The contact opening 110, which is typically cylindrical in shape, comprises a rim 111, a bottom 112, and a wall 113 within the dielectric 101. Underlying the bottom 112 of the contact opening 110 is an active component 120 with a contact surface 122. In order to achieve electrical conductivity between the tungsten plug to be formed and the active component 120, the contact plug bottom 112 is actually the contact surface 122 of the active component 120. The active component 120 may be the source or drain, or gate region of a conventional semiconductor device. The surface upon which the next layer is to be deposited comprises a surface 103 of the dielectric 101 in addition to the contact surface 122 and the contact wall 113.
After forming the contact opening 110 in the dielectric 101 by conventional processes, the process proceeds with the deposition of an adhesion/barrier layer of Ti/TiN on the dielectric surface 103, contact bottom 112 and wall 113. A titanium layer 114 of a field thickness 116a is deposited by physical vapor deposition (PVD) on the contact surface 122, the contact wall 113, and the dielectric surface 103, which may be any of the conventional insulators used in semiconductor manufacturing. Next a titanium nitride layer 115 of a field thickness 116b is deposited by PVD upon the titanium layer 114. For improved contact resistance, enhanced Ti/TiN coverage of the contact surface 122 is achieved using collimation techniques during PVD. In an advantageous embodiment, a combined thickness 116 of the Ti/TiN layer 114, 115 on the dielectric surface 103 is about 75 nm to about 150 nm. As is shown in FIG. 1A, the Ti/TiN layers 114, 115 near the rim 111 of the contact opening 110 are quite thin in relation to the other portions of the Ti/TiN layers 114, 115. Because of the irregular topography of the wafer's surface 103, 113, 122, the PVD process deposits more Ti/TiN on the uppermost exposed surface 103 of the dielectric 101 than on the contact surface 122 or the contact wall 113. Therefore, a 100 nm field thickness 116 on the exposed dielectric surface 103 results in a Ti/TiN layer thickness 117 of 20 nm on the contact surface 122. As a consequence of the collimated PVD process, the wall 113 of the contact opening 110 acquires a Ti/TiN layer thickness 118 of about 5 nm to 10 nm. Therefore, the PVD process of depositing layers of titanium and titanium nitride results in a contact plug bottom thickness 117 with about 20% of the field thickness 116, while the contact plug wall thickness 118 is about 5% to 10% of the field thickness 116. The coated substrate is then optimally subjected to a rapid thermal anneal (RTA). Then a nucleation or seed layer of tungsten silicide is applied by silane reduction of tungsten hexaflouride (WF6) at a relatively low pressure.
Following deposition of the TiN layer, the manufacturing process then proceeds with the blanket chemical vapor deposition of a layer of tungsten that fills the remaining void of the contact opening 110. Tungsten deposition by CVD, the normal process used, involves the use of WF6, and subjects the exposed surfaces to fluorine gas and hydrofluoric acid. Referring now to FIG. 1B, diffusion of fluorine gas into pinhole defects in the TiN layer 115, especially at the contact plug rim 111 where the TiN layer 115 is thinnest, allows the reaction of fluorine with titanium causing the formation of titanium fluoride. The titanium fluoride formation causes the separation of the TiN layer 115 from the Ti layer 114 and a failure 119 to form, as discussed in M. Rutten, et al, Proceedings of the Conference on Advanced Metalization for ULSI Applications, Murray Hill, Oct. 19, 1991, pages 277 to 283, Materials Research Society. In this case, the TiN peels back to form irregular nuclei 130 around which tungsten will form during the subsequent deposition. Consequently, the TiN failure 119 causes an excessive tungsten growth 135 at the location of the defect when compared to tungsten deposition in the contact opening 110 or on the surface 103. Because of their eruption-like form, the excessive tungsten growths 135 are commonly known as volcanoes.
Referring now to FIG. 2 with continuing reference to FIG. 1B, illustrated is a schematic representation of an exemplary conventional large aspect ratio contact opening 210 formed in a dielectric 201 of a sub-0.25 micron integrated circuit. Conventional processes address W-plug formation in contact openings with small aspect ratios. To prevent TiN layer defects 119 and the formation of volcanoes 135, large aspect ratio contacts require greater TiN field thicknesses 216b, i.e., ≧75 nm, to achieve a desired bottom thickness 217. These thicker TiN films 215 have increased intrinsic stress, especially when the TiN is deposited at lower temperatures or is collimated. When combined with the thermal stress of the RTA, the thick TiN film 215 intrinsic stresses increase the likelihood that the TiN layer 215 will crack 218 at a microscopic level when annealed. These cracks can cause additional nucleation sites for tungsten growth as previously discussed. In the worst cases, high stresses can cause Ti/TiN stack delamination 219, lack of W-plug adhesion, and ultimately device failure.
However, beyond the referenced usage for sealing minor pinhole imperfections in the TiN layer 215, RTA has the additional highly desirable effect that titanium silicide (TiSix) forms at the titanium/dielectric interface 222. The presence of titanium silicide is well known to improve the contact resistance within the contact window 210.
Accordingly, what is needed in the art is a method of fabricating a tungsten plug that enjoys the improved contact resistance in the contact window provided by RTA without inducing failure of the TiN layer.